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參數(shù)資料
型號(hào)： XR19L222IL64-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 23/53頁(yè)
文件大小： 0K
描述： IC UART/TXRX RS232 64QFN
標(biāo)準(zhǔn)包裝： 260
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232
電源電壓： 3.3 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 托盤
XR19L222
3
REV. 1.0.1
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
PIN DESCRIPTIONS
Pin Descriptions
NAME
64-QFN
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE (CMOS/TTL Voltage Levels)
A2
A1
A0
37
38
39
I
Address bus lines [2:0]. These 3 address lines select one of the internal registers in the
UART during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
7
6
5
64
63
59
58
57
I/O
Data bus lines [7:0] (bidirectional).
IOR#
(NC)
23
I
When I/M# pin is HIGH, the Intel bus interface is selected and this input becomes read
strobe (active LOW). The falling edge instigates an internal read cycle and retrieves the
data byte from an internal register pointed by the address lines [A2:A0], puts the data byte
on the data bus to allow the host processor to read it on the rising edge.
When I/M# pin is LOW, the Motorola bus interface is selected and this input is not used.
IOW#
(R/W#)
20
I
When I/M# pin is HIGH, it selects Intel bus interface and this input becomes write strobe
(active LOW). The falling edge instigates the internal write cycle and the rising edge trans-
fers the data byte on the data bus to an internal register pointed by the address lines.
When I/M# pin is LOW, the Motorola bus interface is selected and this input becomes read
(HIGH) and write (LOW) signal.
CSA#
(CS#)
11
I
When I/M# pin is HIGH, this input is chip select A (active low) to enable channel A in the
device.
When I/M# pin is LOW, this input becomes the chip select (active low) for the Motorola bus
interface.
CSB#
(A3)
12
I
When I/M# pin is HIGH, this input is chip select B (active low) to enable channel B in the
device.
When I/M# pin is LOW, this input becomes address line A3 which is used for channel selec-
tion in the Motorola bus interface. Input logic 0 selects channel A and logic 1 selects chan-
nel B.
INTA
(IRQ#)
43
O
(OD)
When I/M# pin is HIGH, it selects Intel bus interface and this output become the active
HIGH device interrupt output for channel A. This output is enabled through the software set-
ting of MCR[3]: set to the active mode when MCR[3] is set to a logic 1, and set to the three
state mode when MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output becomes the active
LOW, open-drain interrupt output for both channels. An external pull-up resistor is required
for proper operation. MCR[3] must be set to a logic 0 for proper operation of the interrupt.
INTB
(NC)
42
O
(OD)
When I/M# pin is HIGH, it selects Intel bus interface and this output become the active
HIGH device interrupt output for channel B. This output is enabled through the software set-
ting of MCR[3]: set to the active mode when MCR[3] is set to a logic 1, and set to the three
state mode when MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output is not used and can
be left unconnected.
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