參數(shù)資料
型號(hào)： XR19L220IL40-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 17/43頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR19L202 40QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR19L220
24
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select (Legacy)
This bit has no function and should be left at ’0’.
FCR[5:4]: Transmit FIFO Trigger Select
(’00’ = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 8 below shows the selections. EFR bit-4 must
be set to ‘1’ before these bits can be accessed.
FCR[7:6]: Receive FIFO Trigger Select
(’00’ = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 8 shows the selections.
4.7
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
TABLE 8: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT
-4
RECEIVE
TRIGGER LEVEL
TRANSMIT
TRIGGER LEVEL
COMPATIBILITY
0
1
0
1
0
1
1 (default)
4
8
14
16L580 and 16C580 compatible.
0
1
0
1
0
1
1 (default)
4
8
14
16L580, 16C550, 16C580, 16C554,
16C2550 and 16C2552 compatible
BIT-1
BIT-0
WORD LENGTH
0
5 (default)
0
1
6
1
0
7
1
8
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