參數(shù)資料
型號： XR19L210IL40-F
廠商： Exar Corporation
文件頁數(shù)： 19/43頁
文件大?。?/td> 0K
描述： IC UART/TXRX RS232 40QFN
標(biāo)準(zhǔn)包裝： 490
特點： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
規(guī)程： RS232
電源電壓： 3 V ~ 5.5 V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN 裸露焊盤（6x6）
包裝： 托盤
XR19L210
26
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced LOW).
This condition remains, until disabled by setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) LOW for alerting the remote receiver of a line break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
4.8
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# output is not available as an output on this device. But for 16C550 compatibility, it can still be used
in internal loopback mode.
Logic 0 = Force DTR output HIGH (default).
Logic 1 = Force DTR output LOW.
MCR[1]: RTS Output
The RTS pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
Logic 0 = Force RTS output HIGH (default).
Logic 1 = Force RTS output LOW.
MCR[2]: OP1# (legacy term)
The OP1# output is not available on the XR19L210, however, it is available in internal loopback. In the Internal
Loopback Mode, this bit controls the state of the modem input RI bit in the MSR register as shown in
Logic 0 = OP1# is HIGH (default).
Logic 1 = OP1# is LOW.
In the Internal Loopback Mode, this bit controls the state of the modem input RI bit in the MSR register as
shown in Figure 11.
MCR[3]: INT Output Enable or OP2# (legacy term)
This bit enables and disables the operation of interrupt output, INT in the Intel mode. If INT output is not used,
OP2# can be used as a general purpose output in the Intel mode. In the Motorola mode, this bit must be set to
logic 0.
Logic 0 = INT output disabled (three state mode) in Intel mode (default).
Logic 1 = INT output enabled (active mode) in Intel mode.
In the Internal Loopback Mode, this bit functions like the OP2# in the 16C550 and is used to set the state of the
modem input CD bit in the MSR register.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 11.
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