REV. 1.0.3 HIGH PERFORMANCE QUAD PCI-EXPRESS UART LSR[3]: Receive Data Framing Error Flag " />
參數(shù)資料
型號(hào)： XR17V354IB-E8-EVB
廠商： Exar Corporation
文件頁(yè)數(shù)： 51/66頁(yè)
文件大?。?/td> 0K
描述： EVAL BRD FOR XR17V354-E8 176BGA
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR17V354
已供物品： 板
其它名稱： 1016-1613
XR17V354IB-E8-EVB-ND
XR17V354
55
REV. 1.0.3
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
LSR[3]: Receive Data Framing Error Flag
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[2]: Receive Data Parity Error Flag
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR (top of the FIFO) does not have correct parity
information and is suspect. This error is associated with the character available for reading in RHR.
LSR[1]: Receiver Overrun Flag
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
4.10
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits
are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general
purpose inputs/outputs when they are not used with modem signals.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit [3] in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit [2] in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
DSR# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS/DSR bit (EFR bit [6]=1) and RTS/DTR flow control select bit (MCR bit [2]=1). Auto CTS/DSR flow control
allows starting and stopping of local data transmissions based on the modem DSR# signal. A HIGH on the
DSR# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW
will resume data transmission. Normally MSR bit [5] is the complement of the DSR# input. However in the
loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a
general purpose input when the modem interface is not used.
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS/DSR bit (EFR bit [6]=1) and RTS/DTR flow control select bit (MCR bit [2]=0). Auto CTS/DSR flow control
allows starting and stopping of local data transmissions based on the modem CTS# signal. A HIGH on the
CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW
will resume data transmission. Normally MSR bit [4] is the complement of the CTS# input. However in the
loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a
general purpose input when the modem interface is not used.
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