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參數(shù)資料
| 型號： | XR17V258IVTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 69/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART PCI BUS OCTAL 144LQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 特點： | * |
| 通道數(shù)： | 8 |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 3.3V，5V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 帶卷 (TR) |
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XR17V258
9
REV. 1.0.2
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
1.0 XR17V258 INTERNAL REGISTERS
The XR17V258 UART has three different sets of registers as shown in Figure 3. The PCI Local Bus
Configuration Space Registers are for plug-and-play auto-configuration when connecting the device to the
PCI bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI
local bus specification. The second register set is the Device Configuration Registers that are also
accessible directly from the PCI bus for programming general operating conditions of the device and
monitoring the status of various functions common to all eight channels. These functions include all 8 channel
UARTs’ interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/
outputs control and status, sleep mode, soft-reset, and device identification and revision. And lastly, each
UART channel has its own set of internal UART Configuration Registers for its own operation control and
status reporting. All 8 sets of channel registers are embedded inside the device configuration registers space,
which provides faster access. The second and third set of registers are mapped into 4K of the PCI bus memory
address space. The following paragraphs describe all 3 sets of registers in detail.
FIGURE 3. THE XR17V258 REGISTER SETS
C hannel 0
IN T , M PIO ,
TIM ER ,REG
D evice C onfig ur ation and
U AR T [7:0]
C onfig ur ation
R eg ister s ar e mapped on
to the Base Addr ess
R eg ister ( BAR ) in a 4K-
byte of memor y addr ess
space
PC I Local Bus
Inter face
C hannel 0
C hannel 1
C hannel 2
C hannel 3
C hannel 4
C hannel 5
C hannel 6
C hannel 7
D evice
C onfig ur ation R eg ister s
8 channel
Inter r upts,
M ultipur pose
I/O s,
16- bit
T imer /C ounter ,
Sleep, R eset, D VID , D R EV
U AR T [7:0]
C onfig ur ation
Reg ister s
16550 C ompatible and EXAR
Enhanced
R eg ister s
PC I Local Bus
C onfig ur ation
Space
R eg ister s for Plug -
and- Play
Auto
C onfig ur ation
PCI REG S-1
Vendor
and Sub- vendor
ID
and Pr oduct M odel N umber
in Exter nal EEPR O M
0x00 00
0x02 00
0x04 00
0x06 00
0x08 00
0x0A 0 0
0x0C 00
0x0E00
0x00 80
0x0F F F
1.1
PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
The PCI local bus configuration space registers are responsible for setting up the device’s operating
environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus
plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data
from every device/card on the bus, it defines and downloads the memory mapping information to each device/
card about their individual operation memory address location and conditions. The operating memory mapped
address location is downloaded into the Base Address Register (BAR) register, located at an address offset of
0x10 in the configuration space. Custom modification of certain registers is possible by using an external
93C46 EEPROM. The EEPROM contains the device vendor and sub-vendor data, along with 6 other words of
information (see “Section 1.4, EEPROM Interface” on page 14) required by the auto-configuration setup.
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