參數(shù)資料
型號(hào)： XR17D158
廠商： Exar Corporation
英文描述： UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
中文描述： 通用（3.3V和5V）PCI總線八進(jìn)制的UART
文件頁(yè)數(shù)： 39/72頁(yè)
文件大?。?/td> 1520K
代理商： XR17D158
xr
REV. 1.2.1
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
XR17D158
39
N
OTE
:
MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR17D158. They are present for 16C550
compatibility during Internal loopback, see
Figure 18
.
5.8
Registers
5.8.1
Receive Holding Register (RHR) - Read-Only
See
“Section 5.3, Receiver” on page 32
for complete details.
5.8.2
Transmit Holding Register (THR) - Write-Only
See
“Section 5.2, Transmitter” on page 30
for complete details.
5.8.3
Baud Rate Generator Divisors (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter and
receiver. The baud rate is programmed through registers DLL and DLM which are only accessible when LCR
bit-7 is set to logic 1. See
“Section 5.1, Programmable Baud Rate Generator” on page 29
for more detail.
0 1 1 1
SPR
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
User Data
1 0 0 0
FCTR
R/W
TRG
Table
Bit-1
TRG
Table
Bit-0
Auto
RS485
Enable
Invert IR
RX Input
RTS/DTR
Hyst Bit-3
RTS/DTR
Hyst Bit-2
RTS/DTR
Hyst Bit-1
RTS/DTR
Hyst Bit-0
1 0 0 1
EFR
R/W
Auto
CTS/DSR
Enable
Auto
RTS/DTR
Enable
Special
Char
Select
Enable
IER [7:5],
ISR [5:4],
FCR[5:4],
MCR[7:5,2]
MSR[7:4]
Software
Flow Cntl
Bit-3
Software
Flow Cntl
Bit-2
Software
Flow Cntl
Bit-1
Software
Flow Cntl
Bit-0
1 0 1 0
TXCNT
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 0
TXTRG
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 1
RXCNT
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 1
RXTRG
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 0 0
XCHAR
R
0
0
0
0
0
0
Xon Det.
Indicator
Xoff Det.
Indicator
Self-clear
after read
1 1 0 0
XOFF1
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 0 1
XOFF2
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1 0
XON1
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1 1
XON2
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
T
ABLE
13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
S
HADED
BITS
ARE
ENABLED
BY
EFR B
IT
-4.
A
DDRESS
A3-A0
R
EG
N
AME
R
EAD
/
W
RITE
B
IT
-7
B
IT
-6
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
C
OMMENT
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