REV. 1.2.2 18 TIMER [15:8] - Reserved TIMERMSB [31:24] and TIMERLSB [23:16] TIMERMSB and " />
參數(shù)資料
型號(hào): XR17D154CV-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 10/69頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR17D154 144TQFP
標(biāo)準(zhǔn)包裝: 1
系列: *
XR17D154
xr
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. 1.2.2
18
TIMER [15:8] - Reserved
TIMERMSB [31:24] and TIMERLSB [23:16]
TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the
TIMERLSB with most-significant-bit being bit [7] in TIMERMSB. Notice that these registers do not hold the
current counter value when read. Reading the TIMERCNTL register will clear its interrupt. Default value is
zero (timer disabled) upon powerup and reset.
2.2.3
8XMODE [7:0] - (default 0x00)
Each bit selects 8X or 16X sampling rate for that UART channel, bit-0 is channel 0. Logic 0 (default) selects
normal 16X sampling with logic one selects 8X sampling rate. Transmit and receive data rates will double by
selecting 8X.
2.2.4
REGA [15:8] Reserved
2.2.5
RESET [23:16] - (default 0x00)
The 8-bit Reset register [RESET] provides the software with the ability to reset the UART(s) when there is a
need. Each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. All registers in that
channel will be reset to the default condition, see Table 20 for details. Bit-0 =1 resets UART channel 0 with bit-
3=1 resets channel 3..
TIMERCNTL Register
Rsvd
MPIO[0]
Control
Clock
Select
Single/
Re-trigger
Start/
Stop
INT
Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2
Bit-1 Bit-0
TIMERMSB Register
Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10
Bit-9 Bit-8
TIMERLSB Register
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1 Bit-0
16-Bit Timer/Counter Programmable Registers
Rsvd
Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0
8XMODE Register
Individual UART Channel 8X Clock Mode Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Rsvd
Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0
RESET Register
Individual UART Channel Reset Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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