REV. 1.3.2 5V PCI BUS QUAD UART 27 4.2.3 Transmitter Operation in FIFO mode The host may fill the transmit FIFO with up to 64 bytes" />
參數(shù)資料
型號(hào)： XR17C154CV-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 20/62頁(yè)
文件大小： 0K
描述： IC UART PCI BUS QUAD 144LQFP
標(biāo)準(zhǔn)包裝： 60
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 5V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤(pán)
xr
XR17C154
REV. 1.3.2
5V PCI BUS QUAD UART
27
4.2.3
Transmitter Operation in FIFO mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit empty
interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit-5=1) the source of the transmit
empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not
changed until the last stop bit of the last character is shifted out.
4.2.4
Auto RS485 Operation
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit-5. While transmitting, the RTS# or DTR# signal is HIGH. The RTS# or DTR# signal changes from HIGH to
LOW after a specified delay indicated in MSR[7:4] following the last stop bit of the last character that has been
transmitted. This helps in turning around the transceiver to receive the remote station’s response. The delay
optimizes the time needed for the last transmission to reach the farthest station on a long cable network before
switching off the line driver. This delay prevents undesirable line signal disturbance that causes signal
degradation. It also changes the transmitter empty interrupt to TSR empty instead of THR empty.
FIGURE 10. TRANSMITTER OPERATION IN NON-FIFO MODE
FIGURE 11. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X or 8X
Clock
(8XMODE
Register)
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below Programmed Trigger
Level (TXTRG) and then
when becomes empty. FIFO
is Enabled by FCR bit-0=1
Transmit
FIFO
(64-Byte)
TXFIFO1
16X or 8X Clock
(8XMODE Register)
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
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參數(shù)描述
XR17C154CVTR-F 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17C154CVTR-F
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XR17C154IV-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17C154IVTR-F 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17C154IVTR-F
XR17C158 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:5V PCI BUS OCTAL UART
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