參數(shù)資料
型號: XR17C152CM-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 15/62頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR17C152 100TQFP
標準包裝: 1
系列: *
XR17C152
á
5V PCI BUS DUAL UART
REV. 1.2.0
22
3.1.2
Special Rx FIFO Data Unloading at locations 0x180 (channel 0) and 0x380 (channel 1)
The XR17C152 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x180 (channel 0) and 0x380 (channel 1). The entire RX data along with the status can be
downloaded in a single PCI Burst Read operation of 32 DWORD reads. The Status and Data bytes must be
read in 16 or 32 bits format to maintain data integrity. The following tables show this clearly.
3.1.3
Tx FIFO Data Loading at locations 0x100 (channel 0) and 0x300 (channel 1)
The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation
(maximum 16 DWORD writes) at memory locations 0x100 (channel 0) and 0x300 (channel 1).
READ RX FIFO,
WITH LSR
ERRORS
BYTE 3
BYTE 2BYTE 1BYTE 0
Read n+0 to n+1
FIFO Data n+1
LSR n+1
FIFO Data n+0
LSR n+0
Read n+2 to n+3
FIFO Data n+3
LSR n+3
FIFO Data n+2
LSR n+2
Etc
WRITE TX FIFO
BYTE 3
BYTE 2BYTE 1BYTE 0
Write n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Write n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
PCI Bus
Data Bit-31
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
Receive Data Byte n+3
Receive Data Byte n+2
Receive Data Byte n+1
Receive Data Byte n+0
PCI Bus
Data Bit-0
Channel 0 to 1 ReceiveData in 32-bit alignment through the Configuration Register Address
0x0100 and 0x0300
PCI Bus
Data Bit-31
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
Receive Data Byte n+1
Line Status Register n+1
Receive Data Byte n+0
Line Status Register n+0
PCI Bus
Data Bit-0
Channel 0 to 1 Receive Data with Line Status Register in a 32-bit alignment through
the Configuration Register Address 0x0180 and 0x0380
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