- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1975 > XR16V698IQ100-F (Exar Corporation)IC UART FIFO 32B OCTAL 100QFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XR16V698IQ100-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 5/58頁 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 32B OCTAL 100QFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 8 |
| FIFO's： | 32 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.25 V ~ 3.6 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-QFP（14x20） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
XR16V698
13
REV. 1.0.3
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
2.9
THR and RHR Register Locations
The THR and RHR register addresses for channel 0 to channel 7 are shown in Table 5 below. The THR and
RHR for channels 0 to 7 are located at address 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60 and 0x70
respectively. Transmit data byte is loaded to the THR when writing to that address and receive data is
unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550
compatible in 8-bit format, so each bus operation can only write or read in bytes.
FIGURE 7. RECEIVER OPERATION IN NON-FIFO MODE
FIGURE 8. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO 1
16X or 8X or 4X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X or 4X Clock
Error
T
a
gs
(64-
sets)
E
rro
rT
a
g
s
i
n
LSR
bi
ts
4:
2
32 bytes by 11-bit
wide
FIFO
Receive Data Characters
FIFO Trigger=16
Example:
- RX FIFO trigger level selected at 16 bytes
(See Note Below)
Data fills to 24
Data falls to 8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16V794IV-F | IC UART FIFO 64B QUAD 64LQFP |
| XR16V798IQ-F | IC UART FIFO 64B OCTAL 100QFP |
| XR17C152IM-F | IC UART PCI BUS DUAL 100TQFP |
| XR17C154IV | IC UART PCI BUS QUAD 144LQFP |
| XR17C158IV-F | IC UART PCI BUS OCTAL 144LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16V698IQ100TR-F | 制造商:Exar Corporation 功能描述:UART 8-CH 32Byte FIFO 2.5V/3.3V 100-Pin PQFP T/R 制造商:Exar Corporation 功能描述:XR16V698IQ100TR-F |
| XR16V794 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL |
| XR16V794_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL |
| XR16V794IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL |
| XR16V794IV-0A-EVB | 功能描述:UART 接口集成電路 Supports V794 64 ld TQFP,ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。