REV. 1.0.4 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 s" />
參數(shù)資料
型號(hào)： XR16V564IV-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 26/54頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 32B QUAD 64LQFP
標(biāo)準(zhǔn)包裝： 160
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 32 字節(jié)
規(guī)程： RS232
電源電壓： 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
XR16V564/564D
32
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO
REV. 1.0.4
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
LCR BIT-5 = LOW, parity is not forced (default).
LCR BIT-5 = HIGH and LCR BIT-4 = LOW, parity bit is forced to a logical 1 for the transmit and receive data.
LCR BIT-5 = HIGH and LCR BIT-4 = LOW, parity bit is forced to a logical 0 for the transmit and receive data.
TABLE 13: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
0
No parity
0
1
Odd parity
0
1
Even parity
1
0
1
Force parity to mark, HIGH
1
Forced parity to space, LOW
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, LOW, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM/DLD) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
4.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
Logic 0 = Force RTS# output HIGH (default).
Logic 1 = Force RTS# output LOW.
MCR[2]: Reserved
OP1# is not available as an output pin on the V564. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
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