參數資料
| 型號： | XR16V2751IM-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 6/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 64B DUAL 48TQFP |
| 標準包裝： | 250 |
| 特點： | * |
| 通道數： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.25 V ~ 3.6 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調制解調器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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XR16V2751
14
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE
REV. 1.0.1
2.11.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.11.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
2.11.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE
FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X or 8X
Clock
(EMSR Bit-7)
Transm it Data Shift Register
(TSR)
Transm it
Data Byte
THR Interrupt (ISR bit-1) falls
below the program m ed Trigger
Level and then when becom es
em pty. FIFO is Enabled by FCR
bit-0=1
Transm it
FIFO
16X or 8X Clock
(EM SR bit-7)
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
TXF IF O 1
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