NAME 3" />
參數(shù)資料
型號(hào)： XR16V2750IM-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 23/52頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR V2750 48TQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16V2750
3
REV. 1.0.3
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
NAME
32-QFN
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
18
19
20
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
2
1
32
31
30
29
28
27
3
2
1
48
47
46
45
44
I/O
Data bus lines [7:0] (bidirectional).
IOR#
14
19
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
IOW#
12
15
I
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CSA#
7
10
I
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
CSB#
8
11
I
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
INTA
22
30
O
UART channel A Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
INTB
21
29
O
UART channel B Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
TXRDYA#
-
43
O
UART channel A Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel A. See
Table 2. If it is not
used, leave it unconnected.
RXRDYA#
-
31
O
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. See
Table 2. If it is not
used, leave it unconnected.
TXRDYB#
-
6
O
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
Table 3. If it is not
used, leave it unconnected.
相關(guān)PDF資料
PDF描述
VE-JVT-EZ-S CONVERTER MOD DC/DC 6.5V 25W
UPM1A681MPD6TD CAP ALUM 680UF 10V 20% RADIAL
GMM11DSEH-S13 CONN EDGECARD 22POS .156 EXTEND
XR16V2750IL-0B-EB EVAL BOARD FOR V2750 32QFN
S1812R-274K INDUCTOR SHIELDED 270UH SMD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16V2750IM-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16V2750IMTR-F 功能描述:UART 接口集成電路 W/64 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16V2751 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE
XR16V2751_07 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE
XR16V2751_0709 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*