REV. 1.0.2 2.20 Internal Loopback The V2650 UART provides an internal loopb" />
參數(shù)資料
型號(hào)： XR16V2650IM-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 13/47頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR V2650 48TQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16V2650
20
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
REV. 1.0.2
2.20
Internal Loopback
The V2650 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 12 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR#, CD# and RI# inputs are ignored.
Caution: the RX input pin must be held HIGH during loopback test, else upon exiting the loopback test the
UART may detect and report a false “break” signal. Also, auto RTS/CTS flow control is not supported during
internal loopback.
FIGURE 12. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
Mo
dem
/G
en
eral
P
ur
po
se
Cont
rol
L
og
ic
Inte
rna
lData
Bus
Lin
es
a
nd
Control
S
igna
ls
RTSA#/RTSB#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB#
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
OP2A#/OP2B#
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