REV. 1.0.3 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface i" />
參數(shù)資料
型號： XR16V2550IL-F
廠商： Exar Corporation
文件頁數(shù)： 44/46頁
文件大小： 0K
描述： IC UART FIFO 16B DUAL 32QFN
標準包裝： 490
特點： *
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422
電源電壓： 2.25 V ~ 3.6 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應商設備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 托盤
XR16V2550
7
REV. 1.0.3
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The V2550 data interface supports the Intel compatible types of CPUs and it is compatible
to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data
bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels
share the same data bus for host operations. The data bus interconnections are shown in Figure 3.
FIGURE 3. XR16V2550 DATA BUS INTERCONNECTIONS
VCC
OP2A#
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
OP2B#
DSRB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
CDB#
GND
A0
A1
A2
UART_CSA#
UART_CSB#
IOR#
IOW #
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW #
UART
Channel A
UART
Channel B
UART_INTB
UART_INTA
INTB
INTA
RXRDYA#
TXRDYA#
RXRDYA#
TXRDYA#
RXRDYB#
TXRDYB#
RXRDYB#
TXRDYB#
UART_RESET
RESET
Serial Interface of
RS-232, RS-422
Serial Interface of
RS-232, RS-422
2.2
5-Volt Tolerant Inputs
The V2550 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the V2550 is
operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial
transceiver that is operating at 5V.
2.3
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 15). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
2.4
Device Identification and Revision
The XR16V2550 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DVID will
provide 0x02 for the XR16V2550 and reading the content of DREV will provide the revision of the part; for
example, a reading of 0x01 means revision A.
2.5
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A LOW signal on the chip select pins, CSA# or CSB#,
allows the user to select UART channel A or B to configure, send transmit data and/or unload receive data to/
from the UART. Selecting both UARTs can be useful during power up initialization to write to the same internal
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