REV. 1.0.3 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. RTSB# 15 " />
參數(shù)資料
型號(hào): XR16V2550IL-0B-EB
廠商: Exar Corporation
文件頁(yè)數(shù): 42/46頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR V2550 32QFN
標(biāo)準(zhǔn)包裝: 1
系列: *
XR16V2550
5
REV. 1.0.3
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
RTSB#
15
22
O
UART channel B Request-to-Send (active low) or general purpose out-
put. This port must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1], and IER[6].
CTSB#
16
23
I
UART channel B Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
DTRB#
-
35
O
UART channel B Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
DSRB#
-
20
I
UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
CDB#
-
16
I
UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
RIB#
-
21
I
UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
OP2B#
-
9
O
Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is set to
the three state mode and OP2B# output HIGH when MCR[3] is set to a
logic 0. See MCR[3]. If INTB is used, this output should not be used as
a general output else it will disturb the INTB output functionality.
ANCILLARY SIGNALS
XTAL1
10
13
I
Crystal or external clock input.
XTAL2
11
14
O
Crystal or buffered clock output.
RESET
24
36
I
Reset (active high) - A longer than 40 ns HIGH pulse on this pin will
reset the internal registers and all outputs. The UART transmitter output
will be held HIGH, the receiver input will be ignored and outputs are
reset during reset period (see
VCC
26
42
Pwr
2.25V to 3.6V power supply. All input pins are 5V tolerant.
GND
13
17
Pwr
Power supply common, ground.
GND
Center Pad
N/A
Pwr
The center pad on the backside of the 32-QFN package is metallic and
should be connected to GND on the PCB. The thermal pad size on the
PCB should be the approximate size of this center pad and should be
solder mask defined. The solder mask opening should be at least
0.0025" inwards from the edge of the PCB thermal pad.
NC
9, 17
12, 24, 25,
37
No Connection.
Pin Description
NAME
32-QFN
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
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