REV. 1.0.2 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 4.5 FIFO Control Register (FCR) - Write-Only This r" />
參數(shù)資料
型號： XR16M770IB25-F
廠商： Exar Corporation
文件頁數(shù)： 22/52頁
文件大小： 0K
描述： IC UART FIFO 64B 25BGA
標(biāo)準(zhǔn)包裝： 714
特點： *
通道數(shù)： 1，UART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 25-WFBGA
供應(yīng)商設(shè)備封裝： 25-BGA（3x3）
包裝： 托盤
XR16M770
29
REV. 1.0.2
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
enable the wake up interrupt. They are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: Enable wake up interrupt (requires EFR bit-4 = 1)
Logic 0 = Disable the wake up interrupt (default).
Logic 1 = Enable the wake up interrupt.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4 = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 9 below shows the selections. Note that the
receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to
both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 9 shows the complete selections.
Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last
applies to both the RX and TX side.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16M770IB25TR-F 制造商:Exar Corporation 功能描述:UART 1-CH 64Byte FIFO 1.8V/2.5V/3.3V 25-Pin VFBGA T/R 制造商:Exar Corporation 功能描述:XR16M770IB25TR-F
XR16M770IL24 制造商:EXAR 制造商全稱:EXAR 功能描述:1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
XR16M770IL24-0B-EB 功能描述:界面開發(fā)工具 Eval Board for XR16M770IL24 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XR16M770IL24-0C-EB 功能描述:界面開發(fā)工具 Eval Board for XR16M770IL24 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XR16M770IL24-F 功能描述:UART 接口集成電路 1.8 HIGH PERFORMANCE UART W/64 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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