REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.2 Device Reset The RESET input resets the internal reg" />
參數(shù)資料
型號： XR16M752IM-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 3/54頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR 16M752-B 48TQFP
標準包裝： 1
系列： *
XR16M752/XR68M752
11
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.2
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
2.3
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. During Intel Bus Mode (16/68# pin connected to VCC), a
logic 0 on chip select pins, CSA# or CSB#, allows the user to select UART channel A or B to configure, send
transmit data and/or unload receive data to/from the UART. Selecting both UARTs can be useful during power
up initialization to write to the same internal registers, but do not attempt to read from both UARTs
simultaneously. Individual channel select functions are shown in Table 1.
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE
FUNCTION
1
UART de-selected
0
1
Channel A selected
1
0
Channel B selected
0
Channel A and B selected
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the M752 decodes an
additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in
the Motorola Bus Mode. See Table 2.
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE
FUNCTION
1
N/A
UART de-selected
0
Channel A selected
0
1
Channel B selected
2.4
Channel A and B Internal Registers
Each UART channel in the M752 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM/DLD), and a user accessible Scratchpad Register (SPR).
Beyond the general 16C550 features and capabilities, the M752 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, TCR, TLR and DLD) that provide automatic RTS and CTS hardware flow control, Xon/Xoff
software flow control, automatic RS-485 half-duplex direction output enable/disable, and programmable FIFO
trigger level control. All the register functions are discussed in full detail later in “Section 3.0, UART Internal
CSA#
CSB#
CS#
A3
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