REV. 1.1.1 3.0 UART INTERNAL REGISTERS Each of the UART channel in the M752 has i" />
參數(shù)資料
型號： XR16M752IL-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 17/54頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR 16M752-B 32QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16M752/XR68M752
24
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.1.1
3.0 UART INTERNAL REGISTERS
Each of the UART channel in the M752 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CSA# or CSB# selecting the channel. The complete register set is shown on Table 7 and
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS
ADDRESSES
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0 0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0 0 0
DLL - Divisor LSB
Read/Write
LCR[7] = 1, LCR
≠ 0xBF
0 0 1
DLM - Divisor MSB
Read/Write
0 1 0
DLD - Divisor Fractional
Read/Write
LCR[7] = 1, LCR
≠ 0xBF,
EFR[4] = 1
0 0 1
IER - Interrupt Enable Register
Read/Write
LCR[7] = 0
0 1 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0 1 1
LCR - Line Control Register
Read/Write
1 0 0
MCR - Modem Control Register
Read/Write
LCR
≠ 0xBF
1 0 1
LSR - Line Status Register
Read-only
1 1 0
MSR - Modem Status Register
Read-only
See
1 1 1
SPR - Scratch Pad Register
Read/Write
See
1 1 0
TCR - Transmission Control Register
Read/Write
See
1 1 1
TLR - Trigger Level Register
Read/Write
See
1 1 1
FIFO Rdy - FIFO Ready Register
Read-only
See
ENHANCED REGISTERS
0 1 0
EFR - Enhanced Function Register
Read/Write
LCR = 0xBF
1 0 0
Xon-1 - Xon Character 1
Read/Write
1 0 1
Xon-2 - Xon Character 2
Read/Write
1 1 0
Xoff-1 - Xoff Character 1
Read/Write
1 1 1
Xoff-2 - Xoff Character 2
Read/Write
A2 A1 A0
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