參數(shù)資料
型號(hào): XR16M654IQ100-F
廠(chǎng)商: Exar Corporation
文件頁(yè)數(shù): 26/58頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 64B QUAD 100QFP
標(biāo)準(zhǔn)包裝: 66
特點(diǎn): *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS232
電源電壓: 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-BQFP
供應(yīng)商設(shè)備封裝: 100-QFP(14x20)
包裝: 托盤(pán)
XR16M654/654D
32
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.0
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the -TXRDY and -RXRDY pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4 = 1)
(logic 0 = default, TX trigger level = one)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 12 below shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 12 shows the complete selections.
TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT
-4
RECEIVE
TRIGGER
LEVEL
TRANSMIT
TRIGGER
LEVEL
0
1
0
1
0
1
0
1
0
1
0
1
8
16
56
60
8
16
32
56
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