REV. 1.0.1 1.62V TO 3.63V UART WITH 16-BYTE FIFO AND VLIO INTERFACE 4.13 Baud Rate Generator Registers (DLL, DLM and DLD)" />
參數(shù)資料
型號(hào)： XR16M581IL24-0C-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 31/51頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR16M581-C 24QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16M581
37
REV. 1.0.1
1.62V TO 3.63V UART WITH 16-BYTE FIFO AND VLIO INTERFACE
4.13
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
These registers make-up the value of the baud rate divisor. The M581 has different DLL, DLM and DLD for
transmitter and receiver. It provides more convenience for the transmitter and receiver to transmit data with
different rate. The M581 uses DLD[7:6] to select TX or RX. Then it provides DLD[5:0] to select the sampling
frequency and fractional baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit
divisor value. The value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. See Table 13 below and See ”Section 2.7, Programmable
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 13 below.
TABLE 13: SAMPLING RATE SELECT
SAMPLING RATE
0
16X
0
1
8X
1
X
4X
DLD[6]: Independent BRG enable
Logic 0 = The Transmitter and Receiver uses the same Baud Rate Generator. (default).
Logic 1 = The Transmitter and Receiver uses different Baud Rate Generators. Use DLD[7] for selecting
which baud rate generator to configure.
DLD[7]: BRG select
When DLD[6] = 1, this bit selects whether the values written to DLL, DLM and DLD[5:0] will be for the Transmit
Baud Rate Generator or the Receive Baud Rate Generator. When DLD[6] = 0 (same Baud Rate Generator
used for both TX and RX), this bit must be a logic 0 to properly write to the appropriate DLL, DLM and
DLD[5:0]. .
TABLE 14: BRG SELECT
0
Transmitter and Receiver uses same BRG.
Writing to DLL, DLM and DLD[5:0] configures the BRG for both the TX and RX.
0
1
Transmitter and Receiver uses different BRGs.
Writing to DLL, DLM and DLD[5:0] configures the BRG for TX.
1
Transmitter and Receiver uses different BRGs.
Writing to DLL, DLM and DLD[5:0] configures the BRG for RX.
1
0
Transmitter and Receiver uses same BRG.
Writing to DLL, DLM and DLD[5:0] has no effect on BRG used by the TX and RX.
DLD[5]
DLD[4]
DLD[7]
DLD[6]
BRG
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