REV. 1.0.2 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each of the UART channel in the M2550 " />
參數(shù)資料
型號: XR16M2550IM48-F
廠商: Exar Corporation
文件頁數(shù): 14/47頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B 1.8V DL 48TQFP
產(chǎn)品培訓(xùn)模塊: UART Product Overview
標(biāo)準(zhǔn)包裝: 250
特點: *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 2.25 V ~ 3.6 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
其它名稱: 1016-1286
XR16M2550
21
REV. 1.0.2
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO
3.0 UART INTERNAL REGISTERS
Each of the UART channel in the M2550 has its own set of configuration registers selected by address lines
A0, A1 and A2 with CSA# or CSB# selecting the channel. The complete register set is shown on Table 8 and
TABLE 8: UART CHANNEL A AND B UART INTERNAL REGISTERS
ADDRESSES
A2 A1 A0
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0 0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0 0 0
DLL - Divisor LSB
Read/Write
LCR[7] = 1, LCR
≠ 0xBF
0 0 1
DLM - Divisor MSB
Read/Write
0 1 0
DLD - Divisor Fractional
Read/Write
LCR[7] = 1, LCR
≠ 0xBF,
EFR[4] = 1
0 0 0
DREV - Device Revision Code
Read-only
DLL, DLM
= 0x00,
LCR[7] = 1, LCR
≠ 0xBF
0 0 1
DVID - Device Identification Code
Read-only
0 0 1
IER - Interrupt Enable Register
Read/Write
LCR[7] = 0
0 1 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
LCR
≠ 0xBF
0 1 1
LCR - Line Control Register
Read/Write
1 0 0
MCR - Modem Control Register
Read/Write
LCR
≠ 0xBF
1 0 1
LSR - Line Status Register
Read-only
1 1 0
MSR - Modem Status Register
Read-only
1 1 1
SPR - Scratch Pad Register
Read/Write
ENHANCED REGISTERS
0 1 0
EFR - Enhanced Function Register
Read/Write
LCR = 0xBF
1 0 0
Xon-1 - Xon Character 1
Read/Write
1 0 1
Xon-2 - Xon Character 2
Read/Write
1 1 0
Xoff-1 - Xoff Character 1
Read/Write
1 1 1
Xoff-2 - Xoff Character 2
Read/Write
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