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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | XR16M2550IL32-F |
| 寤犲晢锛� | Exar Corporation |
| 鏂囦欢闋佹暩(sh霉)锛� | 19/47闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC UART FIFO 16B 1.8V DUAL 32QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | UART Product Overview |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 490 |
| 鐗归粸(di菐n)锛� | * |
| 閫氶亾鏁�(sh霉)锛� | 2锛孌UART |
| FIFO's锛� | 16 瀛楃瘈(ji茅) |
| 瑕�(gu墨)绋嬶細 | RS232锛孯S422 |
| 闆绘簮闆诲锛� | 2.25 V ~ 3.6 V |
| 甯惰嚜鍕�(d貌ng)娴侀噺鎺у埗鍔熻兘锛� | 鏄� |
| 甯禝rDA 绶ㄧ⒓鍣�/瑙ｇ⒓鍣細 | 鏄� |
| 甯舵晠闅滃暉鍕�(d貌ng)浣嶆娓姛鑳斤細 | 鏄� |
| 甯惰(di脿o)鍒惰В瑾�(di脿o)鍣ㄦ帶鍒跺姛鑳斤細 | 鏄� |
| 甯禖MOS锛� | 鏄� |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 32-VFQFN 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 32-QFN 瑁搁湶鐒婄洡锛�5x5锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鍏跺畠鍚嶇ū锛� | 1016-1285 |
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XR16M2550
26
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO
REV. 1.0.2
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. If it is a special
character interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is
received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has been de-
asserted.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Receive Data Time-out)
3
0
1
0
RXRDY (Received Data Ready)
4
0
1
0
TXRDY (Transmit Ready)
5
0
MSR (Modem Status Register)
6
0
1
0
RXRDY (Received Xoff or Special character)
7
1
0
CTS#, RTS# change of state
-
0
1
None (default)
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| XR16M2551IL32-F | IC UART FIFO 16B DUAL 32QFN |
| XR16M2650IM48-F | IC UART FIFO 32B DUAL 48TQFP |
| XR16M2651IM48-F | IC UART FIFO 32B DUAL 48TQFP |
| XR16M2750IM48-F | IC UART FIFO 64B DUAL 48TQFP |
| XR16M2751IM48-F | IC UART FIFO 64B DUAL 48TQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| XR16M2550IM-0B-EB | 鍔熻兘鎻忚堪:鐣岄潰闁嬬櫦(f膩)宸ュ叿 Supports M2550 48 ld TQFP, PCI Interface RoHS:鍚� 鍒堕€犲晢:Bourns 鐢�(ch菐n)鍝�:Evaluation Boards 椤炲瀷:RS-485 宸ュ叿鐢ㄤ簬瑭�(p铆ng)浼�:ADM3485E 鎺ュ彛椤炲瀷:RS-485 宸ヤ綔闆绘簮闆诲:3.3 V |
| XR16M2550IM48 | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪: 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪: |
| XR16M2550IM48-F | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 1.62V-3.63V 16B FIFO temp -45 to 85C RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
| XR16M2551 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE |
| XR16M2551IL-0B-EB | 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 Supports M2551 32pin QFN, PCI Interface RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel |
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