參數(shù)資料
型號(hào)： XR16L788
廠商： Exar Corporation
英文描述： HIGH PERFORMANCE OCTAL UART
中文描述： 高性能八進(jìn)制的UART
文件頁(yè)數(shù)： 30/42頁(yè)
文件大?。?/td> 557K
代理商： XR16L788
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XR16L788 OCTAL UART
REV. 1.1.4
30
FCTR[4]: Infrared RX Input Logic Select
0 = Select RX input as active high encoded IrDA data,
normal, (default).
1 = Select RX input as active low encoded IrDA data,
inverted.
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
0 = Standard ST16C550 mode. Transmitter gener-
ates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register
(TSR) may still be shifting data bit out.
1 = Enable Auto RS485 half duplex direction con-
trol. RTS# output changes its logic level from 1 to 0
when finished sending the last stop bit of the last
character out of the TSR register. It changes back
to logic level 1 from 0 when a data byte is loaded
into the THR or transmit FIFO. The change to logic
1 occurs prior sending the start-bit. It also changes
the transmitter interrupt from transmit holding to
transmit shift register (TSR) empty.
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trig-
ger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set
to "next FIFO trigger level" for compatibility to
ST16C550 and ST16C650 series. RTS/DTR# trig-
gers on the next level of the RX FIFO trigger level, in
another word, one FIFO level above and one FIFO
level below. See in
Table 10
for complete selection
with FCR bit 4-5 and FCTR bit 6-7, i.e. if Table C is
used on the receiver with RX FIFO trigger level set to
56 bytes, RTS/DTR# output will de-assert at 60 and
re-assert at 16.
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this
register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
Table 14). When the Xon1 and Xon2 and Xoff1 and
Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential characters. Cau-
tion: note that whenever changing the TX or RX flow
control bits, always reset all bits back to logic 0 (dis-
able) before programming a new setting.
T
ABLE
13: 16 S
ELECTABLE
H
YSTERESIS
L
EVELS
W
HEN
T
RIGGER
T
ABLE
-D
IS
S
ELECTED
FCTR B
IT
-
3
FCTR B
IT
-
2
FCTR B
IT
-
1
FCTR B
IT
-
0
RTS/DTR H
YSTERESIS
(
CHARACTERS
)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+/- 4
+/- 6
+/- 8
+/- 8
+/- 16
+/- 24
+/- 32
+/- 12
+/- 20
+/- 28
+/- 36
+/- 40
+/- 44
+/- 48
+/- 52
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