參數(shù)資料
型號： XR16L784
廠商： Exar Corporation
英文描述： HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
中文描述： 高性能2.97V至5.5V UART的四
文件頁數(shù)： 38/52頁
文件大小： 625K
代理商： XR16L784
XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
á
REV. 1.2.0
38
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550
and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one
FIFO level above and one FIFO level below. See in
Table 14
for complete selection with FCR bit 4-5 and FCTR
bit 6-7, i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR# output will
de-assert at 60 and re-assert at 16.
4.13
Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
Table 18
). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the
new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with ST16C554 mode (default).
T
ABLE
18: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
EFR
BIT
-3
C
ONT
-3
EFR
BIT
-2
C
ONT
-2
EFR
BIT
-1
C
ONT
-1
EFR
BIT
-0
C
ONT
-0
T
RANSMIT
AND
R
ECEIVE
S
OFTWARE
F
LOW
C
ONTROL
0
0
0
0
No TX and RX flow control (default and reset)
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1/Xoff1
0
1
X
X
Transmit Xon2/Xoff2
1
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1/Xoff1
X
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
1
Transmit Xon1/ Xoff1,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2/Xoff2,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
相關(guān)PDF資料
PDF描述
XR16L78464-TQFP HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
XR16L784CV HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
XR16L784IV HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
XR16L788 HIGH PERFORMANCE OCTAL UART
XR16L788CQ HIGH PERFORMANCE OCTAL UART
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16L784_05 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
XR16L784_08 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
XR16L78464-TQFP 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
XR16L784CV 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
XR16L784CV-0A-EVB 功能描述:UART 接口集成電路 Supports L784 64 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*