參數(shù)資料
型號: XR16L580IM
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
中文描述: 1 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁數(shù): 30/47頁
文件大?。?/td> 285K
代理商: XR16L580IM
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
á
REV. 1.2.0
30
LSR[3]: Receive Data Framing Error Flag
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the
character available for reading in RHR.
LSR[4]: Receive Break Flag
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the FIFO
mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to
the idle condition, “mark” or logic 1.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
Logic 0 = No FIFO error (default).
Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or
break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the RX
FIFO.
4.10
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.
MSR[0]: Delta CTS# Input Flag
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt will be
generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt will be
generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
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