參數(shù)資料
型號: XR16L580
廠商: Exar Corporation
英文描述: SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
中文描述: 2.25V至5.5V的最小的16字節(jié)FIFO和省電的UART
文件頁數(shù): 28/47頁
文件大?。?/td> 285K
代理商: XR16L580
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
á
REV. 1.2.0
28
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line break
condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
4.8
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Invert Infrared RX Data or OP1# (legacy term)
If IrDA mode is enabled by setting MCR[6]=1 and if EFR[4] = 1, this bit acts as ’Invert Infrared RX data’
command. If EFR[4] = 0 or in internal loopback mode, this bit functions like the OP1# in the 16C550.
Logic 0 = Select RX input as active-low encoded IrDA data (if IrDA Mode is enabled by setting MCR[6] = 1 and
EFR[4] = 1) (default).
Logic 1 = Select RX input as active-high encoded IrDA data (if MCR[6] = 1 and EFR[4] = 1). In this mode, this bit is
write-only.
In the Internal Loopback Mode, this bit controls the state of the modem input RI# bit in the MSR register as
shown in Figure 13.
T
ABLE
9: P
ARITY
SELECTION
LCR B
IT
-5 LCR B
IT
-4 LCR B
IT
-3
P
ARITY
SELECTION
X
X
0
No parity
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
Force parity to mark,
“1”
1
1
1
Forced parity to
space, “0”
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