參數(shù)資料
型號(hào): XR16L570IL32TR-F
廠商: Exar Corporation
文件頁(yè)數(shù): 47/47頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 16B 32QFN
標(biāo)準(zhǔn)包裝: 3,000
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 1.62 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 帶卷 (TR)
XR16L570
9
REV. 1.0.1
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
2.9
Programmable Baud Rate Generator
The L570 UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit (bit-7) in the MCR register. This bit selects the prescaler to divide the input external clock by a
factor of 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a
programmable divisor (via DLL and DLM registers) between 1 and (216 -1) to obtain a 16X sampling rate clock
of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver for
data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon power
up.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate. Table 3 shows the standard data rates available with a 14.7456 MHz external clock at 16X
sampling rate clock rate. When using a non-standard data rate external clock, the divisor value can be
calculated for DLL/DLM with the following equation.
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER
divisor (decimal) = (clock frequency / prescaler) / (serial data rate x 16)
CLK
Clock
Buffer
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
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