參數(shù)資料
型號: XR16L2751CM
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
中文描述: 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁數(shù): 7/52頁
文件大?。?/td> 618K
代理商: XR16L2751CM
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
á
7
auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has
to set FCTR[3] = 1. This pin is normally high for receive state, low for transmit state.
Data Bus Interface, Intel or Motorola Type
The 2751 provides a single host interface for the 2 UARTs and supports Intel or Motorola microprocessor
(CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type
of CPUs using IOR#, IOW# and CSA# or CSB# inputs for data bus operation. The Motorola bus compatible
interface instead uses the R/W#, CS# and A3 signals for data bus transactions. Few data bus interface signals
change their functions depending on user’s selection, see pin description for details. The Intel and Motorola
bus interface selection is made through the pin, 16/68#, pin 24.
Data Rate
Each channel in the 2751 is capable of operation up to 3.125 Mbps at 5V, 2 Mbps at 3.3V and 1 Mbps at 2.5V
supply with 16X internal sampling clock rate, and 6.25 Mbps at 5V, 4 Mbps at 3.3V and 2 Mbps at 2.5V with 8X
sampling clock rate. The device can operate with an external 24 MHz crystal on pins XTAL1 and XTAL2, or
external clock source of up to 50 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a
software option, the user can set the prescaler bit for data rates of up to 1.84 Mbps.
Internal Enhanced Register Sets
Each UART has a set of enhanced registers providing control and monitoring functions for interrupt enable/
disable and status, FIFO enable/disable, programmable TX and RX FIFO trigger level, TX and RX FIFO level
counters, automatic hardware/software flow control enable/disable with selectable hysteresis, automatic RS-
485 half-duplex direction control output enable/disable, programmable baud rates, infrared encoder/decoder
enable/disable, modem interface controls and status, and sleep mode are all standard features. Following a
power on reset or an external reset, the registers defaults to the reset condition and its is compatible with
previous generation of UARTs, 16C450, 16C550, 16C650A and 16C850.
2.0
FUNCTIONAL DESCRIPTIONS
2.1
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2751 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CSA/B#, IOR# and IOW# or CS#, R/W# and A3 inputs.
Both UART channels share the same data bus for host operations. A typical data bus interconnection for Intel
and Motorola mode is shown in
Figure 3
.
CPU Interface
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