REV. 1.2.3 12 2.10 Programmable Baud Rate Generator Each UART has i" />
參數(shù)資料
型號： XR16L2751CM-F
廠商： Exar Corporation
文件頁數(shù)： 4/50頁
文件大?。?/td> 0K
描述： IC UART FIFO 64B DUAL 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.25 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
其它名稱： 1016-1451
XR16L2751CM-F-ND
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.2.3
12
2.10
Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by CLKSEL
hardware pin or a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input
crystal or external clock by 1 or 4 and can override the CLKSEL pin following reset. The clock output of the
prescaler goes to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (216 -
1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter
for data bit shifting and receiver for data sampling. The BRG divisor defaults to the maximum baud rate (DLL =
0x01 and DLM = 0x00) upon power up.
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate. Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X sampling rate clock rate. A 16X sampling clock is typically used. However, user can select the 8X
sampling clock rate mode (EMSR bit-7=0) to double the operating data rate. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16XMode [EMSR bit-7] = 1
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), with 16XMode [EMSR bit-7] = 0
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=1
OUTPUT Data Rate
MCR Bit-7=0
(DEFAULT)
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
PROGRAM
VALUE (HEX)
PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
115.2k
460.8k
2
02
00
02
0
230.4k
921.6k
1
01
00
01
0
DLM
DLL
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