- 您現(xiàn)在的位置：買賣IC網 > PDF目錄376454 > XR16L2552IM (EXAR CORP) 2.25V TO 5.5V DUART WITH 16-BYTE FIFO PDF資料下載
參數(shù)資料
| 型號： | XR16L2552IM |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2.25V TO 5.5V DUART WITH 16-BYTE FIFO |
| 中文描述： | 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, TQFP-48 |
| 文件頁數(shù)： | 32/47頁 |
| 文件大?。?/td> | 748K |
| 代理商： | XR16L2552IM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
xr
REV. 1.1.1
32
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
Logic 0 = No concurrent write (default).
Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
AFR[2:1]: MF# Output Select
These bits select a signal function for output on the MF# A/B pins. These signal function are described as:
OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.
AFR[7:3]: Reserved
All are initialized to logic 0.
4.14
Device Identification Register (DVID) - Read Only
This register contains the device ID (0x02 for XR16L2552). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.15
Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.16
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
Table 12
). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
B
IT
-2
B
IT
-1
MF# F
UNCTION
0
0
OP2# (default)
0
1
BAUDOUT#
1
0
RXRDY#
1
1
Reserved
相關PDF資料 |
PDF描述 |
|---|---|
| XR16L2552 | 2.25V TO 5.5V DUART WITH 16-BYTE FIFO |
| XR16L2750CJ | 2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| XR16L2750CM | 2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| XR16L2750IJ | 2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| XR16L2750IM | 2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR16L2552IM-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L2552IMTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 16Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16L2552IMTR-F |
| XR16L2750 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| XR16L2750_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| XR16L2750CJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
發(fā)布緊急采購，3分鐘左右您將得到回復。