參數(shù)資料
型號: XR16L2551IL
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: LOW VOLTAGE DUART WITH POWERSAVE
中文描述: 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, QCC32
封裝: 5 X 5 MM, 0.90 MM HEIGHT, QFN-32
文件頁數(shù): 9/48頁
文件大?。?/td> 287K
代理商: XR16L2551IL
á
REV. 1.0.0
XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
9
2.3
The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to
their default state (see
Table 14
). An active high pulse of at least 40 ns duration will be required to activate the
reset function in the device.
2.4
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external CPU
and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the user to
select UART channel A or B to configure, send transmit data and/or unload receive data to/from the UART.
Selecting both UARTs can be useful during power up initialization to write to the same internal registers, but do
not attempt to read from both uarts simultaneously. Individual channel select functions are shown in
Table 1
.
Device Reset
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the L2551 decodes an
additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in
the Motorola Bus Mode.
See Table 2
.
Channel A and B Internal Registers
Each UART channel in the L2551 has a standard register set for controlling, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratch pad register (SPR).
2.5
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the L2551 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show
their behavior. Also see
Figure 20
through
Figure 25
.
T
ABLE
1: C
HANNEL
A
AND
B S
ELECT
IN
16 M
ODE
CSA#
CSB#
F
UNCTION
1
0
1
0
1
1
0
0
UART de-selected
Channel A selected
Channel B selected
Channel A and B selected
T
ABLE
2: C
HANNEL
A
AND
B S
ELECT
IN
68 M
ODE
CS#
A3
F
UNCTION
1
0
0
N/A
0
1
UART de-selected
Channel A selected
Channel B selected
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XR16L2551IM 制造商:EXAR 制造商全稱:EXAR 功能描述:LOW VOLTAGE DUART WITH POWERSAVE