REV. 1.1.3 LOW VOLTAGE DUART WITH 16-BYTE FIFO Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain. RTSB# 15 27 22 " />
參數(shù)資料
型號(hào)： XR16L2550IMTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 40/44頁(yè)
文件大小： 0K
描述： IC UART FIFO 16B DUAL 48TQFP
標(biāo)準(zhǔn)包裝： 1,500
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
規(guī)程： RS232
電源電壓： 2.25 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 帶卷 (TR)
XR16L2550
5
REV. 1.1.3
LOW VOLTAGE DUART WITH 16-BYTE FIFO
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
RTSB#
15
27
22
O
UART channel B Request-to-Send (active low) or general pur-
pose output. This output must be asserted prior to using auto
RTS flow control, see EFR[6], MCR[1] and IER[6]. If it is not
used, leave it unconnected.
CTSB#
16
28
23
I
UART channel B Clear-to-Send (active low) or general purpose
input. It can be used for auto CTS flow control, see EFR[7] and
IER[7]. This input should be connected to VCC when not used.
DTRB#
-
38
35
O
UART channel B Data-Terminal-Ready (active low) or general
purpose output. If it is not used, leave it unconnected.
DSRB#
-
25
20
I
UART channel B Data-Set-Ready (active low) or general purpose
input. This input should be connected to VCC when not used.
This input has no effect on the UART.
CDB#
-
21
16
I
UART channel B Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used.
This input has no effect on the UART.
RIB#
-
26
21
I
UART channel B Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used.
This input has no effect on the UART.
OP2B#
-
15
9
O
Output Port 2 Channel B - The output state is defined by the user
and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 when MCR[3] is set to
a logic 1. INTB is set to the three state mode and OP2B# to a
logic 1 when MCR[3] is set to a logic 0. This output should not be
used as a general output else it will disturb the INTB output func-
tionality. If it is not used, leave it unconnected.
ANCILLARY SIGNALS
XTAL1
10
18
13
I
Crystal or external clock input.
XTAL2
11
19
14
O
Crystal or buffered clock output.
RESET
24
39
36
I
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin
will reset the internal registers and all outputs. The UART trans-
mitter output will be held at logic 1, the receiver input will be
ignored and outputs are reset during reset period.
VCC
26
44
42
Pwr
2.25V to 5.5V power supply. All inputs are 5V tolerant.
GND
13
22
17
Pwr
Power supply common, ground.
GND
Center
Pad
N/A
Pwr
The center pad on the backside of the 32-QFN package is metal-
lic and should be connected to GND on the PCB. The thermal
pad size on the PCB should be the approximate size of this cen-
ter pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the
PCB thermal pad.
N.C.
9, 17
-
12, 24,
25, 37
No Connection. These pins are open, but typically, should be con-
nected to GND for good design practice.
Pin Description
NAME
32-QFN
PIN #
44-PLCC
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
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