參數(shù)資料
型號(hào)： XR16L2550
廠商： Exar Corporation
英文描述： LOW VOLTAGE DUART WITH 16-BYTE FIFO
中文描述： 低壓杜阿爾特16字節(jié)FIFO
文件頁(yè)數(shù)： 8/45頁(yè)
文件大?。?/td> 278K
代理商： XR16L2550
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
á
REV. 1.0.0
8
2.5
Each UART channel in the L2550 has a standard register set for controlling, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratch pad register (SPR).
2.6
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the L2550 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show
their behavior. Also see
Figure 18
through
Figure 23
.
Channel A and B Internal Registers
2.7
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 3
and
Table 4
summarize the operating behavior for the transmitter and receiver. Also see
Figure 18
through
Figure 23
.
INTA and INTB Outputs
1
0
Channel B selected
0
0
Channel A and B selected
T
ABLE
2: TXRDY#
AND
RXRDY# O
UTPUTS
IN
FIFO
AND
DMA M
ODE
P
INS
FCR
BIT
-0=0
(FIFO D
ISABLED
)
FCR B
IT
-0=1 (FIFO E
NABLED
)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B
0 = 1 byte.
1 = no data.
0 = at least 1 byte in FIFO
1 = FIFO empty.
1 to 0 transition when FIFO reaches the trigger
level, or time-out occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B
0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
T
ABLE
3: INTA
AND
INTB P
INS
O
PERATION
FOR
T
RANSMITTER
FCR B
IT
-0 = 0
(FIFO D
ISABLED
)
FCR B
IT
-0 = 1
(FIFO E
NABLED
)
INTA/B Pin
0 = a byte in THR
1 = THR empty
0 = at least 1 byte in FIFO
1 = FIFO empty
T
ABLE
1: C
HANNEL
A
AND
B S
ELECT
CSA#
CSB#
F
UNCTION
相關(guān)PDF資料
PDF描述
XR16L2551 LOW VOLTAGE DUART WITH POWERSAVE
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