參數(shù)資料
型號(hào): XR16L2450IM
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.25V TO 5.5V DUART
中文描述: 2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁數(shù): 15/30頁
文件大?。?/td> 511K
代理商: XR16L2450IM
xr
REV. 1.1.0
XR16L2450
2.25V TO 5.5V DUART
15
4.4.1
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by data byte received in RHR.
TXRDY is by THR empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
Interrupt Generation:
4.4.2
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data out of RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Interrupt Clearing:
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See
Table 6
).
ISR[7:4]: Reserved
4.5
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
T
ABLE
6: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
P
RIORITY
L
EVEL
ISR R
EGISTER
S
TATUS
B
ITS
S
OURCE
OF
INTERRUPT
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
1
0
1
1
0
LSR (Receiver Line Status Register)
2
0
1
0
0
RXRDY (Received Data Ready)
3
0
0
1
0
TXRDY (Transmit Ready)
4
0
0
0
0
MSR (Modem Status Register)
-
0
0
0
1
None (default)
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