REV. 1.1.1 14 4.3.1 Interrupt Mode Operation When the receive interrupt (IER BIT-0 = 1) is enabled, the RHR in" />
參數(shù)資料
型號(hào)： XR16L2450IJ-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 6/30頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 1B DUAL 44PLCC
標(biāo)準(zhǔn)包裝： 27
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)
規(guī)程： RS232
電源電壓： 2.25 V ~ 5.5 V
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
XR16L2450
xr
2.25V TO 5.5V DUART
REV. 1.1.1
14
4.3.1
Interrupt Mode Operation
When the receive interrupt (IER BIT-0 = 1) is enabled, the RHR interrupt (see ISR bit-2) status will reflect the
following:
A. The receive data available interrupts are issued to the host when there is a character in the RHR. It will be
cleared when the character has been read out of the RHR.
B. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the RHR is empty.
4.3.2
Polled Mode Operation
Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode
by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in the RHR.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the RHR may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the THR and TSR are empty.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If
the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[7:4]: Reserved
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 6, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
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