參數(shù)資料
型號: XR16C854IJ-F
廠商: Exar Corporation
文件頁數(shù): 26/53頁
文件大小: 0K
描述: IC UART FIFO 128B QUAD 68PLCC
標準包裝: 19
特點: *
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應商設(shè)備封裝: 68-PLCC
包裝: 管件
其它名稱: XR16C854IJ-F-ND
XR16C854/854D
32
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REV. 3.1.0
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
4.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved
OP1# is not available as an output pin on the 854. But it is available for use during Internal Loopback Mode. In
the Loopback Mode, this bit is used to write the state of the modem RI# interface signal. If OP1# output is
required for RS485 operation, use the XR16C864.
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL
input, see below table for details. This bit is also used to control the OP2# signal during internal loopback
mode. INTSEL pin must be set to a logic zero during 68 mode.
Logic 0 = INT (A-D) outputs disabled (three state) in the 16 mode (default). During loopback mode, it sets
OP2# internally to a logic 1.
Logic 1 = INT (A-D) outputs enabled (active) in the 16 mode. During loopback mode, it sets OP2# internally
to a logic 0.
TABLE 13: INT OUTPUT MODES
INTSEL
PIN
MCR
BIT-3
INT A-D OUTPUTS IN 16 MODE
0
Three-State
0
1
Active
1
X
Active
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