
XR16C850
xr
2.97V TO 5.5V UART WITH 128-BYTE FIFO
REV. 2.3.1
50
FIGURE 27. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED]
FIGURE 28. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED]
RX
RXRDY#
IOR#
INT
D0:D7
S
T
SSR
RXINTDMA#
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
First Byte is
Received in
RX FIFO
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
RR
T
RRI
T
SSI
(Reading data out
of RX FIFO)
RX
RXRDY#
IOR#
INT
D0:D7
S
T
SSR
RXFIFODMA
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
RR
T
RRI
T
SSI
(Reading data out
of RX FIFO)