REV. 2.1.3 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 49 NOTICE EXAR Corporation reserves the right to make changes to the" />
參數(shù)資料
型號(hào)： XR16C2850IJ-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 44/51頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 128B 44PLCC
標(biāo)準(zhǔn)包裝： 27
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
其它名稱： 1016-1567-5
XR16C2850IJ-F-ND
xr
XR16C2850
REV. 2.1.3
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
49
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet November 2005.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISION HISTORY
Date
Revision
Description
February 2000
Rev 1.0.0
Initial datasheet.
April 2002
Rev 2.0.0
Changed to standard style format. Internal Registers are described in the order they
are listed in the Internal Register Table. Clarified timing diagrams. Corrected Auto
RTS Hysteresis table. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and tim-
ing symbols. Added TAH, TCS and OSC.
May 2004
Rev 2.1.0
Changed to single column format. Added device status to ordering information.
Clarified sleep mode conditions. Clarified pin descriptions- changed from using logic
1 and logic 0 to HIGH (VCC) and LOW (GND) for input and output pin descriptions.
Added VOL sink current and VOH source current charts (
Figure 15). Devices with top mark date code of "F2 YYWW" and newer have 5V
tolerant inputs (except for XTAL1) and have 0 ns address hold time (TAH). DREV reg-
ister was updated to 0x06.
February 2005
Rev 2.1.1
Corrected datasheet to show that all inputs are 5V tolerant (including XTAL1) in
devices with top mark date code of "F2 YYWW" and newer.
August 2005
Rev 2.1.2
Removed discontinued 40-pin PDIP from Ordering Information.
November 2005
Rev 2.1.3
Corrected part numbers in Ordering Information.
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