REV. 2.1.3 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 11 Typical oscillator connections are shown in Figure 4. For further readin" />
參數(shù)資料
型號： XR16C2850CJTR-F
廠商： Exar Corporation
文件頁數(shù)： 3/51頁
文件大?。?/td> 0K
描述： IC UART FIFO 128B 44PLCC
標準包裝： 500
特點： *
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
xr
XR16C2850
REV. 2.1.3
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
11
Typical oscillator connections are shown in Figure 4. For further reading on oscillator circuit please see
application note DAN108 on EXAR’s web site.
2.9
Programmable Baud Rate Generator
A single Baud Rate Generator (BRG) is provided for the transmitter and receiver, allowing independent TX/RX
channel control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of
up to 24 MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2
pin (as shown in Figure 5) it can extend its operation up to 50 MHz (3.125 Mbps serial data rate and 16X
sampling) at room temperature and 5.0V.
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
Each UART also has their own prescaler along with the BRG. The prescaler is controlled by CLKSEL hardware
pin or a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or
external clock by 1 or 4 and can override the CLKSEL pin following reset. The clock output of the prescaler
goes to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (216 -1) to
obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for
data bit shifting and receiver for data sampling.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate. Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X sampling rate clock rate. A 16X sampling clock is typically used. However, user can select the 8X
sampling clock rate mode to double the operating data rate. When using a non-standard data rate crystal or
external clock, the divisor value can be calculated for DLL/DLM with the following equation.
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER
2K
XTAL1
XTAL2
R1
VCC
External Clock
vcc
gnd
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
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