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參數(shù)資料
| 型號： | XR-T7288 |
| 廠商： | Exar Corporation |
| 英文描述： | CEPT1 Line Interface |
| 中文描述： | CEPT1線路接口 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 293K |
| 代理商： | XR-T7288 |
XR-T7288
17
Rev. 1.01
Timing Characteristics
All duty–cycle and timing relationships are in reference to a TTL, 1.4V threshold level.
Loss–of–Clock Indication Timing
The clock must be absent 6.4 s to guarantee a loss–of–clock indication.However, a loss–of–clock indication can occur if
the clock is absent for as little as 1.95
μ
s, depending on the timing relationship of the interruption with respect to the timing
cycle.
The returning clock must be present 3.91
μ
s to guarantee a normal condition on the loss–of–clock pin (LOC). However,
the loss–of–clock indication can return to normal immediately, depending on the timing relationship of the signal return
with respect to the timing cycle.
T
A
= –40
°
C to
±
85
°
C; V
DD
= 5 V
±
10%; load capacitance = 40 pF.
Symbol
Description
Min
Typ
Max
Unit
tTCLTCL
TCLK Clock Period
1
488
1
ns
tTCHTCL
TCLK Duty Cycle
Data Setup Time, TDATA
2
to TCLK
Data Hold Time, TCLK to TDATA
2
40
50
60
%
tTDVTCL
50
ns
tTCLTDV
40
ns
tr
Clock Rise Time (10% 90%)
40
ns
tf
Clock Fall Time (10% 90%)
40
ns
tRCLRCL
RCLK Duty Cycle
Data Hold Time, RCLK to RDATA, VIO
3
Data Setup Time, RDATA, VIO to RCLK
3
Propagation Delay, RCLK to RDATA, VIO
3
40
50
60
%
tRCHRDV
171
ns
tRDVRCH
131
ns
tRCLRDV
40
ns
Table 9. Clock Timing Relationships
Notes
1
A tolerance of 80 ppm.
2
DATA for single–rail mode; TPDATA and TNDATA for dual–rail mode.
3
RDATA and VIO for single–rail mode; RPDATA and RNDATA for dual–rail mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7288IP | 制造商:Exar Corporation 功能描述: 制造商:Exar Corporation 功能描述:DATACOM, PCM TRANSCEIVER, PDIP28 |
| XR-T7288IP | 制造商:EXAR 制造商全稱:EXAR 功能描述:CEPT1 Line Interface |
| XRT7288IW | 制造商:EXAR 制造商全稱:EXAR 功能描述:CEPT1 Line Interface |
| XR-T7288IW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
| XR-T7295 | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/Sonet STS-1 Integrated Line Receiver |
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