參數(shù)資料
型號(hào)： XQ4028EX-4PG191M
廠商： Xilinx, Inc.
英文描述： QML High-Reliability FPGAs
中文描述： QML第高可靠性的FPGA
文件頁數(shù)： 15/36頁
文件大小： 285K
代理商： XQ4028EX-4PG191M
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
15
R
XQ4000E IOB Input Switching Characteristic Guidelines
(continued)
Symbol
Setup Times (TTL Inputs)
(1,2)
Description
Device
-3
-4
Units
Min
Max
Min
Max
T
PICK
T
PICKD
Pad to clock (IK), no delay
All devices
2.6
-
4.0
-
ns
Pad to clock (IK), with delay
XQ4005E
-
-
10.9
-
ns
XQ4010E
9.8
-
11.3
-
ns
XQ4013E
10.2
-
11.8
-
ns
XQ4025E
-
-
14.0
-
ns
Setup Times (CMOS Inputs)
(1,2)
T
PICKC
T
PICKDC
Pad to clock (IK), no delay
All devices
3.3
-
6.0
-
ns
Pad to clock (IK), with delay
XQ4005E
-
-
12.0
-
ns
XQ4010E
10.5
-
13.0
-
ns
XQ4013E
10.9
-
13.5
-
ns
XQ4025E
-
-
16.0
-
ns
(TTL or CMOS)
T
ECIK
T
ECIKD
Clock enable (EC) to clock (IK), no delay
All devices
2.5
-
3.5
-
ns
Clock enable (EC) to clock (IK), with delay
XQ4005E
-
-
10.4
-
ns
XQ4010E
9.7
-
10.7
-
ns
XQ4013E
10.1
-
11.1
-
ns
XQ4025E
-
-
14.0
-
ns
Global Set/Reset
(3)
T
RRI
T
MRW
T
MRI
Notes:
1.
Delay from GSR net through Q to I1, I2
All devices
-
7.8
-
12.0
ns
GSR width
All devices
11.5
-
13.0
-
ns
GSR inactive to first active clock (IK) edge
All devices
11.5
-
13.0
-
ns
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
2.
3.
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