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參數(shù)資料
| 型號： | XQ4005EX-4CB191N |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QML High-Reliability FPGAs |
| 中文描述： | QML第高可靠性的FPGA |
| 文件頁數(shù)： | 29/36頁 |
| 文件大?。?/td> | 285K |
| 代理商： | XQ4005EX-4CB191N |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
29
R
XQ4028EX IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4000EX devices unless otherwise noted.
Symbol
Description
-4
Units
Min
Clocks
T
OKIK
Delay from FCL enable (OK) active to IFF clock (IK) active edge
3.2
ns
Propagation Delays
T
PID
T
PLI
T
PPLI
T
PDLI
T
PFLI
T
PPFLI
Propagation Delays (TTL Inputs)
Pad to I1, I2
2.2
ns
Pad to I1, I2 via transparent input latch, no delay
3.8
ns
Pad to I1, I2 via transparent input latch, partial delay
13.3
ns
Pad to I1, I2 via transparent input latch, full delay
18.2
ns
Pad to I1, I2 via transparent FCL and input latch, no delay
5.3
ns
Pad to I1, I2 via transparent FCL and input latch, partial delay
13.6
ns
T
IKRI
T
IKLI
T
OKLI
Clock (IK) to I1, I2 (flip-flop)
3.0
ns
Clock (IK) to I1, I2 (latch enable, active Low)
3.2
ns
FCL enable (OK) active edge to I1, I2 (via transparent standard input latch)
6.2
ns
Global Set/Reset
T
MRW
T
RRI
Minimum GSR pulse width
13.0
ns
Delay from GSR input to any Q
22.8
ns
Notes:
1.
2.
3.
FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch
For CMOS input levels, see the
"XQ4028EX Input Threshold Adjustments" on page 28
.
For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold
tables on
page 28
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XQ4005EX-3CB191M | QML High-Reliability FPGAs |
| XQ4005EX-3CB191N | QML High-Reliability FPGAs |
| XQ4005EX-3CB196M | QML High-Reliability FPGAs |
| XQ4005EX-3CB196N | QML High-Reliability FPGAs |
| XQ4005EX-3HQ191M | QML High-Reliability FPGAs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ4005EX-4CB196M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005EX-4CB196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005EX-4HQ191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005EX-4HQ191N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4005EX-4HQ196M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
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