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| 型號(hào)： | XQ2V6000-4FG456M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| 中文描述： | QPro的Virtex - II 1.5V的軍事QML第平臺(tái)FPGA |
| 文件頁(yè)數(shù)： | 9/128頁(yè) |
| 文件大小： | 2738K |
| 代理商： | XQ2V6000-4FG456M |
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QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
9
R
The DDR mechanism shown in
Figure 4
can be used to mir-
ror a copy of the clock on the output. This is useful for prop-
agating a clock along the data that has an identical delay. It
is also useful for multiple clock generation, where there is a
unique clock driver for every clock load. Virtex-II devices
can produce many copies of a clock with very little skew.
Each group of two registers has a clock enable signal (ICE
for the input registers, OCE for the output registers, and
TCE for the 3-state registers). The clock enable signals are
active High by default. If left unconnected, the clock enable
for that storage element defaults to the active state.
Each IOB block has common synchronous or asynchronous
set and reset (SR and REV signals).
SR forces the storage element into the state specified by the
SRHIGH or SRLOW attribute. SRHIGH forces a logic “1”.
SRLOW forces a logic “0”. When SR is used, a second input
(REV) forces the storage element into the opposite state. The
reset condition predominates over the set condition. The ini-
tial state after configuration or global initialization state is
defined by a separate INIT0 and INIT1 attribute. By default,
the SRLOW attribute forces INIT0, and the SRHIGH attribute
forces INIT1.
For each storage element, the SRHIGH, SRLOW, INIT0,
and INIT1 attributes are independent. Synchronous or
asynchronous set/reset is consistent in an IOB block.
All the control signals have independent polarities. Any
inverter placed on a control input is automatically absorbed.
Each register or latch (independent of all other registers or
latches) (see
Figure 5
) can be configured as follows:
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
The synchronous reset overrides a set, and an asynchro-
nous clear overrides a preset.
Figure 4:
Double Data Rate Registers
D1
CLK1
DDR MUX
Q1
FDDR
D2
CLK2
(50/50 duty cycle clock)
CLOCK
Q
Q
Q2
D1
CLK1
DDR MUX
DCM
Q1
FDDR
D2
CLK2
Q2
180
°
0
°
DS031_26_100900
ds122_1_1.fm Page 9 Wednesday, January 7, 2004 9:15 PM
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| XQ2V6000-4FG456N | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
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