- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375045 > XQ2V3000-4BG728M (Xilinx, Inc.) QPro Virtex-II 1.5V Military QML Platform FPGAs PDF資料下載
參數(shù)資料
| 型號(hào)： | XQ2V3000-4BG728M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| 中文描述： | QPro的Virtex - II 1.5V的軍事QML第平臺(tái)FPGA |
| 文件頁(yè)數(shù)： | 4/128頁(yè) |
| 文件大?。?/td> | 2738K |
| 代理商： | XQ2V3000-4BG728M |
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
QPro Virtex-II 1.5V Military QML Platform FPGAs
4
www.xilinx.com
1-800-255-7778
DS122 (v1.1) January 7, 2004
Product Specification
R
Configurable Logic Blocks (CLBs)
CLB resources include four slices and two 3-state buffers.
Each slice is equivalent and contains:
Two function generators (F and G)
Two storage elements
Arithmetic logic gates
Large multiplexers
Wide function capability
Fast carry look-ahead chain
Horizontal cascade chain (OR gate)
The function generators F and G are configurable as 4-input
look-up tables (LUTs), as 16-bit shift registers, or as 16-bit
distributed SelectRAM memory.
In addition, the two storage elements are either edge-trig-
gered D-type flip-flops or level-sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
Block SelectRAM Memory
The block SelectRAM memory resources are 18 Kb of
dual-port RAM, programmable from 16K x 1 bit to 512 x 36
bits, in various depth and width configurations. Each port is
totally synchronous and independent, offering three
"read-during-write" modes. Block SelectRAM memory is
cascadable to implement large embedded storage blocks.
Supported memory configurations for dual-port and sin-
gle-port modes are shown in
Table 3
.
A multiplier block is associated with each SelectRAM mem-
ory block. The multiplier block is a dedicated 18 x 18-bit
multiplier and is optimized for operations based on the block
SelectRAM content on one port. The 18 x 18 multiplier can
be used independently of the block SelectRAM resource.
Read/multiply/accumulate operations and DSP filter struc-
tures are extremely efficient.
Both the SelectRAM memory and the multiplier resource
are connected to four switch matrices to access the general
routing resources.
Global Clocking
The DCM and global clock multiplexer buffers provide a
complete solution for designing high-speed clocking
schemes.
Up to 12 DCM blocks are available. To generate de-skewed
internal or external clocks, each DCM can be used to elimi-
nate clock distribution delay. The DCM also provides 90-,
180-, and 270-degree phase-shifted versions of its output
clocks. Fine-grained phase shifting offers high-resolution
phase adjustments in increments of 1/256 of the clock
period. Very flexible frequency synthesis provides a clock
output frequency equal to any M/D ratio of the input clock
frequency, where M and D are two integers. For the exact
timing parameters, see
QPro Virtex-II Switching Charac-
teristics
, page 51
.
Virtex-II devices have 16 global clock MUX buffers with up
to eight clock nets per quadrant. Each global clock MUX
buffer can select one of the two clock inputs and switch
glitch-free from one clock to the other. Each DCM block is
able to drive up to four of the 16 global clock MUX buffers.
Routing Resources
The IOB, CLB, block SelectRAM, multiplier, and DCM ele-
ments all use the same interconnect scheme and the same
access to the global routing matrix. Timing models are
shared, greatly improving the predictability of the perfor-
mance of high-speed designs.
There are a total of 16 global clock lines with eight available
per quadrant. In addition, 24 vertical and horizontal long
lines per row or column as well as massive secondary and
local routing resources provide fast interconnect. Virtex-II
buffered interconnects are relatively unaffected by net
fanout, and the interconnect layout is designed to minimize
crosstalk.
Horizontal and vertical routing resources for each row or
column include:
24 long lines
120 hex lines
40 double lines
16 direct connect lines (total in all four directions)
Boundary Scan
Boundary-scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-II devices that complies with IEEE standards
1149.1 — 1993 and 1532. A system mode and a test mode
are implemented. In system mode, a Virtex-II device per-
forms its intended mission even while executing non-test
boundary-scan instructions. In test mode, boundary-scan
test instructions control the I/O pins for testing purposes.
The Virtex-II Test Access Port (TAP) supports BYPASS,
PRELOAD, SAMPLE, IDCODE, and USERCODE non-test
instructions. The EXTEST, INTEST, and HIGHZ test instruc-
tions are also supported.
Table 3:
Dual-Port And Single-Port Configurations
16K x 1 bit
2K x 9 bits
8K x 2 bits
1K x 18 bits
4K x 4 bits
512 x 36 bits
ds122_1_1.fm Page 4 Wednesday, January 7, 2004 9:15 PM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XQ2V3000-4BG728N | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4CF1144M | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4CF1144N | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4CG717M | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4CG717N | QPro Virtex-II 1.5V Military QML Platform FPGAs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ2V3000-4BG728N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Platform FPGAs |
| XQ2V3000-4CF1144M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4CF1144N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4CG717M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Platform FPGAs |
| XQ2V3000-4CG717N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。