參數(shù)資料
型號(hào)： XQ2V1000-4FG456M
廠商： Xilinx, Inc.
英文描述： QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述： QPro的Virtex - II 1.5V的軍事QML第平臺(tái)FPGA
文件頁數(shù)： 47/128頁
文件大?。?/td> 2738K
代理商： XQ2V1000-4FG456M
QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
47
R
Table 32:
Recommended Operating Conditions
Symbol
Description
Package
Min
Max
Units
V
CCINT
Internal supply voltage relative to GND, T
C
= –55
°
C to +125
°
C
Internal supply voltage relative to GND, T
J
= –55
°
C to +125
°
C
Auxiliary supply voltage relative to GND, T
C
= –55
°
C to +125
°
C
Auxiliary supply voltage relative to GND, T
J
= –55
°
C to +125
°
C
Supply voltage relative to GND, T
C
= –55
°
C to +125
°
C
Supply voltage relative to GND, T
J
= –55
°
C to +125
°
C
Battery voltage relative to GND, T
C
= –55
°
C to +125
°
C
Battery voltage relative to GND, T
J
= –55
°
C to +125
°
C
Ceramic
1.425
1.575
V
Plastic
1.425
1.575
V
V
CCAUX
Ceramic
3.135
3.465
V
Plastic
3.135
3.465
V
V
CCO
Ceramic
1.2
3.6
V
Plastic
1.2
3.6
V
V
BATT
Ceramic
1.0
3.6
V
Plastic
1.0
3.6
V
Notes:
1.
2.
3.
4.
5.
If battery is not used, do not connect V
BATT
.
Recommended maximum voltage droop for V
CCAUX
is 10 mV/ms.
The thresholds for Power On Reset are V
CCINT
> 1.2V, V
CCAUX
> 2.5V, and V
CCO
(Bank 4) > 1.5 V.
Limit the noise at the power supply to be within 200 mV peak-to-peak.
For power bypassing guidelines, see Xilinx Application Note
XAPP623
.
Table 33:
DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Device
Min
Max
Units
V
DRINT
V
DRI
I
REF
I
L
C
IN
I
RPU
I
RPD
I
BATT
Data retention V
CCINT
voltage
Data retention V
CCAUX
voltage
V
REF
current per bank
Input leakage current
All
1.2
V
All
2.5
V
All
–
10
+10
μ
A
All
–
10
+10
μ
A
Input capacitance
All
10
pF
Pad pull-up (when selected) @ V
IN
= 0 V, V
CCO
= 3.3 V (sample tested)
Pad pull-down (when selected) @ V
IN
= 3.6 V (sample tested)
Battery supply current
All
Note 1
250
μ
A
All
Note 1
250
μ
A
All
100
nA
Notes:
1.
Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
ds122_1_1.fm Page 47 Wednesday, January 7, 2004 9:15 PM
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