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QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
33
R
Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in
Figure 39
.
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
Figure 38:
Multipliers (2-column, 4-column, and 6-column)
DS031_39_110403
2
2
2
2
2
2
2
2
Multiplier Blocks
Multiplier Blocks
2
2
Multiplier Blocks
2
2
Figure 39:
Virtex-II Clock Pads
8 clock pads
8 clock pads
Virtex-II
Device
DS031_42_101000
ds122_1_1.fm Page 33 Wednesday, January 7, 2004 9:15 PM