參數(shù)資料
型號(hào): XQ2V1000-4CF1144M
廠商: Xilinx, Inc.
英文描述: QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述: QPro的Virtex - II 1.5V的軍事QML第平臺(tái)FPGA
文件頁數(shù): 60/128頁
文件大?。?/td> 2738K
代理商: XQ2V1000-4CF1144M
QPro Virtex-II 1.5V Military QML Platform FPGAs
60
www.xilinx.com
1-800-255-7778
DS122 (v1.1) January 7, 2004
Product Specification
R
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 46
shows the test setup parameters used for measur-
ing Input standard adjustments (see
Table 43, page 53
).
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (<1 pf) across approximately 4" of FR4
microstrip trace. Standard termination was used for all test-
ing. (See
Virtex-II Platform FPGA User Guide
for details.)
The propagation delay of the 4" trace is characterized sep-
arately and subtracted from the final measurement, and is
therefore not included in the generalized test setup shown in
Figure 51
.
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. (IBIS
models can be found on the web at
http://support.xil-
inx.com/support/sw_ibis.htm
.) Parameters V
REF
, R
REF
,
C
REF
, and V
MEAS
fully describe the test conditions for each
I/O standard. The most accurate prediction of propagation
delay in any given application can be obtained through IBIS
simulation, using the following method:
1.
Simulate the output driver of choice into the generalized
test setup, using values from
Table 47
.
2.
Record the time to V
MEAS
.
3.
Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4.
Record the time to V
MEAS
.
5.
Compare the results of steps 2 and 4. The increase or
decrease in delay should be added to or subtracted
from the I/O Output Standard Adjustment value
(
Table 45
) to yield the actual worst-case propagation
delay (clock-to-input) of the PCB trace.
Table 46:
Input Delay Measurement Methodology
Standard
V
L
(1)
V
H
(1)
V
MEAS
(3,4)
V
REF
(2,4)
LVTTL
0
3.0
1.4
LVCMOS33
0
3.3
1.65
LVCMOS25
0
2.5
1.25
LVCMOS18
0
1.8
0.9
LVCMOS15
0
1.5
0.75
PCI33_3
Per PCI Specification
PCI66_3
Per PCI Specification
PCI-X
Per PCI-X Specification
GTL
V
REF
– 0.2
V
REF
+ 0.2
V
REF
0.80
GTLP
V
REF
– 0.2
V
REF
+ 0.2
V
REF
1.0
HSTL Class I
V
REF
– 0.5
V
REF
+ 0.5
V
REF
0.75
HSTL Class II
V
REF
– 0.5
V
REF
+ 0.5
V
REF
0.75
HSTL Class III
V
REF
– 0.5
V
REF
+ 0.5
V
REF
0.90
HSTL Class IV
V
REF
– 0.5
V
REF
+ 0.5
V
REF
0.90
SSTL3
Class I & II
V
REF
– 1.00
V
REF
+ 1.00
V
REF
1.5
SSTL2
Class I & II
V
REF
– 0.75
V
REF
+ 0.75
V
REF
1.25
AGP-2X
V
REF
(0.2
x
V
CCO
)
V
REF
+
(0.2
x
V
CCO
)
V
REF
Per
AGP
Spec
LVDS25
1.2 – 0.125
1.2 + 0.125
1.2
LVDS33
1.2 – 0.125
1.2 + 0.125
1.2
LVDSEXT25
1.2 – 0.125
1.2 + 0.125
1.2
LVDSEXT33
1.2 – 0.125
1.2 + 0.125
1.2
ULVDS25
0.6 – 0.125
0.6 + 0.125
0.6
LDT25
0.6 – 0.125
0.6 + 0.125
0.6
LVPECL
1.6 – 0.3
1.6 + 0.3
1.6
Notes:
1.
2.
Input waveform switches between V
and V
.
Measurements are made at typical, minimum, and maximum V
values. Reported delays reflect worst case of these measurements.
V
values listed are typical. See
Virtex-II Platform FPGA User
Guide
for min/max specifications.
Input voltage level from which measurement starts.
Note that this is an input voltage reference that bears no relation to
the V
/ V
MEAS
parameters found in IBIS models and/or noted in
Figure 51
.
3.
4.
Figure 51:
Generalized Test Setup
V
REF
R
REF
V
(vMEAS
delay measurement is taken)
C
REF
(probe capacitance)
FPGA Output
ds083-3_06a_092503
ds122_1_1.fm Page 60 Wednesday, January 7, 2004 9:15 PM
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