參數(shù)資料
型號: XPC860DTZP66D4
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Family Hardware Specifications
中文描述: 32-BIT, 66 MHz, RISC PROCESSOR, PBGA357
封裝: PLASTIC, BGA-357
文件頁數(shù): 39/76頁
文件大小: 857K
代理商: XPC860DTZP66D4
MOTOROLA
MPC860 Family Hardware Specifications
39
Bus Signal Timing
Table 9-11 shows the reset timing for the MPC860.
Figure 9-31 shows the reset timing for the data bus configuration.
Table 9-11. Reset Timing
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
R69
CLKOUT to HRESET high
impedance
20.00
20.00
20.00
20.00
ns
R70
CLKOUT to SRESET high
impedance
20.00
20.00
20.00
20.00
ns
R71
RSTCONF pulse width
515.15
425.00
340.00
257.58
ns
R72
R73
Configuration data to HRESET rising
edge setup time
504.55
425.00
350.00
277.27
ns
R74
Configuration data to RSTCONF
rising edge setup time
350.00
350.00
350.00
350.00
ns
R75
Configuration data hold time after
RSTCONF negation
0.00
0.00
0.00
0.00
ns
R76
Configuration data hold time after
HRESET negation
0.00
0.00
0.00
0.00
ns
R77
HRESET and RSTCONF asserted to
data out drive
25.00
25.00
25.00
25.00
ns
R78
RSTCONF negated to data out high
impedance
25.00
25.00
25.00
25.00
ns
R79
CLKOUT of last rising edge before
chip three-state HRESET to data out
high impedance
25.00
25.00
25.00
25.00
ns
R80
DSDI, DSCK setup
90.91
75.00
60.00
45.45
ns
R81
DSDI, DSCK hold time
0.00
0.00
0.00
0.00
ns
R82
SRESET negated to CLKOUT rising
edge for DSDI and DSCK sample
242.42
200.00
160.00
121.21
ns
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