參數(shù)資料
型號: XPC860DTCZP66D4
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Family Hardware Specifications
中文描述: 32-BIT, 66 MHz, RISC PROCESSOR, PBGA357
封裝: PLASTIC, BGA-357
文件頁數(shù): 69/76頁
文件大?。?/td> 857K
代理商: XPC860DTCZP66D4
MOTOROLA
MPC860 Family Hardware Specifications
69
MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
13.4 MII Serial Management Channel Timing
(MII_MDIO, MII_MDC)
Table 13-30 provides information on the MII serial management channel signal timing. The
FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact
upper bound is under investigation.
Figure 13-73 shows the MII serial management channel timing diagram.
Figure 13-73. MII Serial Management Channel Timing Diagram
Table 13-30. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10
MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
0
ns
M11
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
25
ns
M12
MII_MDIO (input) to MII_MDC rising edge setup
10
ns
M13
MII_MDIO (input) to MII_MDC rising edge hold
0
ns
M14
MII_MDC pulse width high
40%
60%
MII_MDC
period
M15
MII_MDC pulse width low
40%
60%
MII_MDC
period
M11
MII_MDC (Output)
MII_MDIO (Output)
M12
M13
MII_MDIO (Input)
M10
M14
MM15
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